Samsung S3C2451X User Manual page 435

S3C2451X RISC MICROPROCESSOR
General Registers
CONTROL REGISTER(CONTROL_REG)
Register
CONTROL_REG 0x4D408000
Field Bit
Reserved [31:1]
R [0]
INTERRUPT ENABLE REGISTER (INTEN_REG)
Register
INTEN_REG 0x4D408004
Field Bit
Reserved [31:11]
CCF [10]
ACF [9]
FIFO_FULL [8]
Reserved [7:1]
FIFO_INT_E [0]
Address R/W
W Control register
Software Reset
Write to this bit results in a one-cycle reset signal to FIMG2D
graphics engine. Every command register and parameter setting
register will be assigned the "Reset Value", and the command FIFO
will be cleared.
Address R/W
R/W Interrupt Enable register
Current Command Finished interrupt enable.
If this bit is set, when the graphics engine finishes the execution of
current command, an interrupt occurs, and the INTP_CMD_FIN flag
in INTC_PEND_REG will be set.
All Commands Finished interrupt enable.
If this bit is set, when the graphics engine finishes the execution of
all commands in the command FIFO, an interrupt occurs, and the
INTP_ALL_FIN flag in INTC_PEND_REG will be set.
Command FIFO Full interrupt enable.
If this bit is set, when command FIFO is full (32 entries), an interrupt
occurs, and the INTP_FULL flag in the interrupt pending register
(INTC_PEND_REG) will be set.
If this bit is set, when the number of entries occupied in command
FIFO is greater or equal to FIFO_INT_LEVEL (in FIFO_INTC_REG),
an interrupt occurs, and the INTP_FIFO_LEVEL flag in the interrupt
pending register (INTC_PEND_REG) will be set.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
2D
Reset Value
0x0
Initial State
0x0
0x0
Reset Value
0x0
Initial State
0x0
0x0
0x0
0x0
0x0
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