Samsung S3C2451X User Manual page 385

S3C2451X RISC MICROPROCESSOR
SSR Bit
DM [5]
HSP [4]
SDE [3]
HFRM [2]
HFSUSP [1]
HFRES [0]
R/W
R DM Data Line State
DM informs the status of D- Line
R Host Speed
0 = Full Speed
1 = High Speed
R/C Speed Detection End.
SDE is set by the core when the HS Detect Handshake
process is ended.
R/C Host Forced Resume.
HFRM is set by the core in suspend state when host sends
resume signaling.
R/C Host Forced Suspend
HFSUSP is set by the core when the SUSPEND signaling
from host is detected.
R/C Host Forced Reset.
HFRES is set by the core when the RESET signaling from
host is detected.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
USB2.0 DEVICE
Initial State
0
0
0
0
0
0
17-13