Samsung S3C2451X User Manual page 630

CAMERA INTERFACE
IMAGE CAPTURE ENABLE REGISTER
Register
CIIMGCPT 0x4D80_00A0
CIIMGCPT
ImgCptEn
ImgCptEn_
CoSc
ImgCptEn_
PrSc (v)
Reserved [28:27]
Cpt_CoDMA_
Sel
Cpt_CoDMA_
RGBFMT
Cpt_CoDMA_
En
Cpt_CoDMA_ [23:19]
Ptr
Cpt_CoDMA_
Mod
[17:10]
Cpt_CoDMA_
Cnt
Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
23-38
Specifications and information herein are subject to change without notice.
Address R/W
RW
Bit
[31] camera interface global capture enable
[30] capture enable for codec scaler. This bit must be zero in
scaler-bypass mode.
[29] capture enable for preview scaler. (applied both Memory
data input path and External camera path in using preview)
This bit must be zero in scaler-bypass mode.
[26] Codec DMA output format
1 : RGB 16/24 bit (Must be Out422_Co=1 ,
Interleave_Co=1)
0 : YCbCr 4:2:2 or 4:2:0
[25] Codec DMA RGB format
1 : RGB 24-bit
0 : RGB 16-bit
[24] Capture codec dma frame control. It is also used for start
signal of Codec image capture. Therefore, it must be set to
'1' if codec image is wanted. or it must be set to '0' if codec
image is not captured.
1 : Enable
0 : Disable
Capture sequence turn-around pointer
[18] Capture codec dma mode
1 : Apply Cpt_CoDMA_Cnt mode (capture
Cpt_CoDMA_Cnt frames along the Cpt_CoDMA_Seq after
Cpt_CoDMA_En becomes high)
0 : Apply Cpt_CoDMA_En mode (capture frames along the
Cpt_CoDMA_Seq during Cpt_CoDMA_En is high)
Wanted number of frames to be captured (when read, you
will see the value of a shadow register which is
downcounted when a frame is captured. That is,
Cpt_CoDMA_Cnt has an initially loaded value still after a
frame is captured.)
[9:0]
Description
Image capture enable command
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial
State
0
0
0
0
0
0
0
0
0
0
0
0
Change
State
O
O
O
X
O
O
X
X
X
X
X