Samsung S3C2451X User Manual page 534

HSMMC CONTROLLER
FORCE EVENT REGISTER FOR ERROR INTERRUPT STATUS
Register
FEERR0
FEERR1
The Force Event Register is not a physically implemented register. Rather, it is an address at which the
Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error
Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set.
Writing 1 : set each bit of the Error Interrupt Status Register
Writing 0 : no effect
Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to
generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be
set.
Name Bit
[15:10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-66
Specifications and information herein are subject to change without notice.
Address
0X4AC00052
0X4A800052
Reserved
Force Event for ADMA Error
1=Interrupt is generated
0=No Interrupt
Force Event for Auto CMD12 Error
1=Interrupt is generated
0=No Interrupt
Reserved
Force Event for Data End Bit Error
1=Interrupt is generated
0=No Interrupt
Force Event for Data CRC Error
1=Interrupt is generated
0=No Interrupt
Force Event for Data Timeout Error
1=Interrupt is generated
0=No Interrupt
Force Event for Command Index Error
1=Interrupt is generated
0=No Interrupt
Force Event for Command End Bit Error
1=Interrupt is generated
0=No Interrupt
Force Event for Command CRC Error
1=Interrupt is generated
0=No Interrupt
R/W Description
WO Force Event Error Interrupt Register
Error Interrupt (Channel 0)
WO Force Event Error Interrupt Register
Error Interrupt (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0
0
0
0
0
0
0
0
0
0x0000
0x0000