Samsung S3C2451X User Manual page 532

HSMMC CONTROLLER
DEBUG REGISTER
Register
DEBUG_0
DEBUG_1
Name Bit
DBGREG [31:0]
CONTROL REGISTER 4
Register
CONTROL4_0 0x4AC0008C
CONTROL4_1 0x4A80008C
Name Bit
Reserved [31:1]
StaBusy [0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-64
Specifications and information herein are subject to change without notice.
Address
0X4AC00088
0X4A800088
Debug Register
Read Only Register for Debug Purpose (RO)
Address R/W
R/W
R/W
-
Status Busy
This bit is "High" when the clock domain crossing (HCLK to SDCLK)
operation is processing. This bit is status bit and Read Only (RO)
R/W
R/W DEBUG register (Channel
0)
R/W DEBUG register (Channel
1)
Description
Description
Control register 4 (Channel 0)
Control register 4 (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Description Reset Value
Not fixed
Not fixed
Initial
Value
Not
fixed
Reset Value
0x0
0x0
Initial
Value
0
0