Samsung S3C2451X User Manual page 386

USB2.0 DEVICE
SYSTEM CONTROL REGISTER (SCR)
This register enables top-level control of the core. MCU should access this register for controls such as Power
saving mode enable/disable.
Register Address
SCR 0x4980_0020
SCR Bit
[31:15]
DTZIEN [14]
[13]
DIEN [12]
[11:9]
EIE [8]
SPDCEN [7]
SPDEN [6]
[5]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-14
Specifications and information herein are subject to change without notice.
R/W
R/W System Control Register
R/W
Reserved
R/W DMA Total Counter Zero Interrupt Enable
0 = Disable
1 = Enable
When set to 1, DMA total counter zero interrupt is
generated.
Reserved
R/W DUAL Interrupt Enable
0 = Disable
1 = Enable
When set to 1, Interrupt is activated until Interrupt source is
cleared.
Reserved
R/W Error Interrupt Enable
This bit must be set to 1 to enable error interrupt.
Speed detection Control Enable
R/W
0: Disable
1: Enable
R/W Speed Detect End Interrupt Enable
When set to 1, Speed detection interrupt is generated.
Reserved
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
Initial State
0
0
0
0
0