Table of Contents
Advertisement
PRODUCT OVERVIEW
SIGNAL DESCRIPTIONS
Signal
Reset, Clock & Power
XTIpll
XTOpll
NC
EPLLCAP
XTIrtc
XTOrtc
CLKOUT[1:0]
nRESET
nRSTOUT
PWREN
nBATT_FLT
OM[4:0]
EXTCLK
Memory Interface (ROM/SRAM/NAND/CF)
RADDR[25:0]
RDATA[15:0]
nRCS[5:0]
nRWE
nROE
nRBE[1:0]
nWAIT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
1-28
Specifications and information herein are subject to change without notice.
Table 1-4. S3C2451X Signal Descriptions
In/Out
AI
Crystal input signals for internal osc circuit.
When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.
If it isn't used, it has to be Low (0V)
AO
Crystal output signals for internal osc circuit.
When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.
If it isn't used, it has to be float
AI
Not connected.
AI
Loop filter capacitor for Extra PLL
AI
32.768 kHz crystal input for RTC. If it isn't used, it has to be High
(VDD_RTC=3.3V).
AO
32.768 kHz crystal output for RTC. If it isn't used, it has to be float.
O
Clock output signal. The CLKSEL of MISCCR(GPIO register) register
configures the clock output mode among the MPLL_CLK, EPLL CLK,
ARMCLK, HCLK, PCLK.
ST
nRESET suspends any operation in progress and places S3C2451X into a
known reset state. For a reset, nRESET must be held to L level for at least 4
OSCin after the processor power has been stabilized.
O
For external device reset control (nRSTOUT = nRESET & nWDTRST &
SW_RESET)
O
core power on-off control signal
I
Probe for battery state (Does not wake up at Sleep mode in case of low
battery state). If it isn't used, it has to be High (3.3V).
I
OM[4:0] set operating modes of S3C2451X
Refer to "S3C2451 OPERATION MODE DESCRIPTION TABLE"
I
External clock source.
When OM[0] = 1, EXTCLK is used for MPLL and EPLL CLK source.
If it isn't used, it has to be Low (0V).
O
RADDR[25:0] (Address Bus) outputs the memory address of the
corresponding bank .
IO
RDATA[15:0] (Data Bus) inputs data during memory read and outputs data
during memory write. The bus width is programmable among 8/16-bit.
O
nRCS[5:0] (Chip Select) are activated when the address of a memory is within
the address region of each bank. The number of access cycles and the bank
size can be programmed.
O
nRWE (Write Enable) indicates that the current bus cycle is a write cycle.
O
nOE (Output Enable) indicates that the current bus cycle is a read cycle.
O
Upper byte/lower byte enable (In case of 16-bit SRAM)
I
nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the
Description
*SW_RESET = nRSTCON of GPIO MISCCR
S3C2451X RISC MICROPROCESSOR
Advertisement
Chapters
Table of Contents
