Samsung S3C2451X User Manual page 420

IIC-BUS INTERFACE
MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER
Register
IICLC0 0x54000010
IICLC1 0x54000110
IICLC0
Bit
IICLC1
Filter enable [2]
SDA output [1:0]
delay
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
18-14
Specifications and information herein are subject to change without notice.
Address R/W
R/W IIC0-Bus multi-master line control register
R/W IIC1-Bus multi-master line control register
IIC-bus filter enable bit.
When SDA port is operating as input, this bit should be High. This
filter can prevent from occurred error by a glitch during double of
PCLK time.
0: Filter disable
1: Filter enable
IIC-Bus SDA line delay length selection bits.
SDA line is delayed as following clock time(PCLK)
00: 0 clocks
10: 10 clocks
Description
Description
01: 5 clocks
11: 15 clocks
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial State
0x00
0x00
0
00