Samsung S3C2451X User Manual page 574

LCD CONTROLLER
Video Main Control 0 Register (Continued)
VIDCON0 Bit
CLKVALUP [12]
CLKVAL_F [11:6]
VCLKEN [5]
CLKDIR [4]
CLKSEL_F [3:2]
ENVID [1:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
22-34
Specifications and information herein are subject to change without notice.
Select CLKVAL_F Update timing control
0 = Always
1 = Start of a frame (Only once per frame)
Determine the rates of VCLK.
VCLK = (HCLK or LCD video Clock) / [CLKVAL+1] ( CLKVAL ≥ 1 )
VCLK Enable Control
0 = Disable
1 = Enable
Select the clock source as direct or divide using CLKVAL_F register.
0 = Direct clock (frequency of VCLK = frequency of Clock source)
1 = Divided using CLKVAL_F
Select the Video Clock source
00 = HCLK
01 = LCD video Clock (from SYSCON EPLL)
10 = reserved
11 = reserved
Video output and the LCD logics enable/disable control.
00 = Disable video signals and logics immediately.
01 = Reserved.
10 = Disable video signals and logics at the end of current frame.
11 = Enable video output and logics.
Note. If set to '10b' in the middle of displaying current frame, the value
of ENVID is still '11b'. However, the LCD functions are disabled at the
end of current frame and the value is changed to '10b'.
S3C2451X RISC MICROPROCESSOR
Description Initial State
0
0
0
0
0
0