Samsung S3C2451X User Manual page 520

HSMMC CONTROLLER
NORMAL INTERRUPT SIGNAL ENABLE REGISTER
This register is used to select which interrupt status is indicated to the Host System as the interrupt. These
status bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Register
NORINTSIGEN0
NORINTSIGEN1
Name Bit
[15]
ENSIGFIA3 [14]
ENSIGFIA2 [13]
ENSIGFIA1 [12]
ENSIGFIA0 [11]
ENSIGRWAI
[10]
T
ENSIGCCS [9]
ENSIGCARD
[8]
INT
ENSIGCARD
[7]
REM
ENSIGCARD
[6]
NS
ENSIGBUFR
[5]
DRDY
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-52
Specifications and information herein are subject to change without notice.
Address
0X4AC00038
0X4A800038
Fixed to 0
The Host Driver shall control error interrupts using the Error Interrupt
Signal Enable register.
FIFO SD Address Pointer Interrupt 3 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 2 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 1 Signal Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 0 Signal Enable
'1' = Enabled
'0' = Masked
Read Wait Interrupt Signal Enable
'1' = Enabled
'0' = Masked
CCS Interrupt Signal Enable
Command Complete Singal Interrupt Status bit is for CE-ATA interface
mode.
'1' = Enabled
'0' = Masked
Card Interrupt Signal Enable
'1' = Enabled
'0' = Masked
Card Removal Signal Enable
'1' = Enabled
'0' = Masked
Card Insertion Signal Enable
'1' = Enabled
'0' = Masked
Buffer Read Ready Signal Enable
'1' = Enabled
'0' = Masked
R/W Description
R/W Normal Interrupt Signal Enable
Register (Channel 0)
R/W Normal Interrupt Signal Enable
Register (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial Value
0x0
0x0
0
0
0
0
0
0
0
0
0
0
0