Samsung S3C2451X User Manual page 69

S3C2451X RISC MICROPROCESSOR
FUNCTIONAL DESCRIPTIONS
The system controller for S3C2451X has three functions, which include the reset management, the clock
generation, and the power management. In this section, the behavior will be described.
RESET MANAGEMENT AND TYPES
S3C2451x has four types of resets and reset controller in system controller can place the system into the
predefined states with one of the following four resets.
•
Hardware Reset – It is generated when nRESET pin is asserted. It is an uncompromised, unmaskable,
and complete reset, which is used when you need no information in system any more.
•
Watchdog Reset – The watchdog timer monitors the device state and generates the watchdog reset when
the state is abnormal.
•
Software Reset – Software can initialize the internal state by writing the special control register (SWRST).
•
Wakeup Reset – When the system wakes up from SLEEP mode, it generates reset signals. And When
the system wakes up from Deep-STOP mode, it generates ARM reset only.
HARDWARE RESET
When S3C2451x is power-ON, the external device must assert nRESET to initialize internal states.
Hardware reset is invoked when the nRESET pin is asserted and all units in the system (except RTC) are
initialized to known states. During the hardware reset, the following actions will occur:
•
All internal registers and ARM926EJ core goes into their pre-defined initial state.
•
All pins get their reset state, and BATT_FLT pin is ignored.
•
The nRSTOUT pin is asserted while the reset is progressed.
When the unmaskable nRESET pin is asserted as low, the internal hardware reset signal is generated. Upon
assertion of nRESET, S3C2451x enters reset state regardless of the previous state. To enter hardware reset
state, nRESET must be held long enough to allow internal stabilization and propagation of the reset state.
Caution: An external power source, regulator, for S3C2451x must be stable prior to the deassertion of nRESET.
Otherwise, it damages to S3C2451x and its operation will not be guaranteed.
Figure 2-2 shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation
within several milliseconds after the power source supplies enough power-level to S3C2451x. Initially, two internal
PLLs (MPLL and EPLL) stop. The nRESET pin should be released after the fully settle-down of the power supply-
level. S3C2451x requires a hazard-free system clock (SYSCLK, ARMCLK, HCLK, and PCLK) to operate properly
when the system reset is released. Since the PLL does not work initially, the PLL input clock (F
SYSCLK instead of the PLL output clock (F
use each PLL. The PLL begins the lockup sequence toward the new frequency only after the S/W configures the
PLL with a new frequency-value. The PLL output is immediately fed to SYSCLK after lock time.
You should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during the
power-up sequence and the crystal oscillation must be settle-down during this period. However, S3C2451x will
explicitly add the crystal oscillator settle-down time (OSCWAIT) when it wakes up from the STOP mode.
The EPLL output clock is directly fed to some special clocks for TFT Controller, I2S, HS-MMC, USB host and
UART. Since the EPLL input clock is initially fed to the input clocks for them, software must configure EPLLCON
register to use the EPLL.
). Software must configure MPLLCON and EPLLCON register to
OUT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER
) is directly fed to
IN
2-3