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S3C2451X RISC MICROPROCESSOR
CODEC STATUS REGISTER
Register
CICOSTATUS
0x4D80_0064
CICOSTATUS
OvFiY_Co
OvFiCb_Co
OvFiCr_Co
VSYNC
[27:26]
FrameCnt_Co
WinOfstEn_Co
FlipMd_Co
[24:23]
ImgCptEn_
CamIf
ImgCptEn_
CoSC
VSYNC
Reserved
[9:1]
FIELD
RGB1 START ADDRESS REGISTER
Register
CIPRCLRSA1
0x4D80_006C
CIPRCLRSA1
CIPRCLRSA1
[31:0]
(v)
Address
R/W
R
Bit
[31]
Overflow state of codec FIFO Y
[30]
Overflow state of codec FIFO Cb
[29]
Overflow state of codec FIFO Cr
[28]
Camera VSYNC (This bit can be referred by CPU for first
SFR setting after external camera muxing. And, it can be
seen in the ITU-R BT 656 mode)
Frame count of codec DMA (This counter value means the
next frame number)
[25]
Window offset enable status
Flip mode of codec DMA
[22]
Image capture enable of camera interface
[21]
Image capture enable of codec path
[20]
External camera VSYNC (polarity inversion was not
adopted.)
Reserved
[0]
Camera FIELD(polarity inversion was adopted)
Address
R/W
RW
Bit
st
RGB 1
frame start address for preview DMA
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Codec path status
Description
Description
st
RGB 1
frame start address for preview DMA
Description
CAMERA INTERFACE
Reset Value
0
Initial
Change
State
State
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
X
0
X
0
X
Reset Value
0
Initial
Change
State
State
0
X
23-31
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