Samsung S3C2451X User Manual page 5

S3C2451X RISC MICROPROCESSOR
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PRODUCT OVERVIEW
INTRODUCTION
This user's manual describes SAMSUNG's S3C2451X 16/32-bit RISC microprocessor. SAMSUNG's S3C2451X
is designed to provide hand-held devices and general applications with low-power, and high-performance micro-
controller solution in small die size. To reduce total system cost, the S3C2451X includes the following
components.
The S3C2451X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier. Its low-
power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2451X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor designed
by Advanced RISC Machines, Ltd. The ARM926EJ implements MMU, AMBA BUS, and Harvard cache
architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2451X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in
this document include:
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Around 400MHz @ 1.3V, 533MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V
mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU
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External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic) and CF/ATA I/F
controller
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LCD controller (up to 256K color) with LCD-dedicated DMA
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8-ch DMA controllers with external request pins
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4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)
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2-ch High Speed SPls
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2 IIC bus interfaces (multi-master support)
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2 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch, port 1 supports 2ch)
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AC97 CODEC Interface
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2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)
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2-ch USB Host controller (ver 1.1 Complaint)/1-ch USB Device controller (ver 2.0 Complaint)
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4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer
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10-ch 12-bit ADC and Touch screen interface
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RTC with calendar function
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Camera interface (Max. 8M pixels input support. 2M pixel input support for scaling)
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174 General Purpose I/O ports / 24-ch external interrupt source
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Power control: Normal, Idle, Stop, Deep Stop and Sleep mode
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On-chip clock generator with PLL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW
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