Samsung S3C2451X User Manual page 311

Risc microprocessor
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S3C2451X RISC MICROPROCESSOR
WATCHDOG TIMER SPECIAL REGISTERS
WATCHDOG TIMER CONTROL (WTCON) REGISTER
The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different
sources, enable/disable interrupts, and enable/disable the watchdog timer output.
The Watchdog timer is used to resume the S3C2451X restart on malfunction after its power on. At this time,
disable the interrupt generation and enable the Watchdog timer output for reset signal.
If controller restart is not desired and if the user wants to use the normal timer only, which is provided by the
Watchdog timer, enable the interrupt generation and disable the Watchdog timer output for reset signal.
Register
WTCON
0x53000000
WTCON
Bit
Prescaler value
[15:8] Prescaler value.
Reserved
[7:6]
Watchdog timer
[5]
Clock select
[4:3]
Interrupt
[2]
generation
Reserved
[1]
Reset
[0]
enable/disable
Note: Initial state of 'Reset enable/disable' is 1(reset enable). If user do not disable this bit, S3C2451 will be
rebooted in about 5.63sec (In the case of PCLK is 12MHz). So at boot loader, this bit should be disabled before
under control of Operating System, or Firmware.
Address
R/W
R/W
Watchdog timer control register
The valid range is from 0 to 255(28-1).
Reserved.
These two bits must be 00 in normal operation.
Enable or disable bit of Watchdog timer.
0 = Disable
1 = Enable
Determine the clock division factor.
00: 16
10: 64
Enable or disable bit of the interrupt.
0 = Disable
1 = Enable
Reserved.
This bit must be 0 in normal operation.
Enable or disable bit of Watchdog timer output for reset signal.
1: Assert reset signal of the S3C2451X at watchdog time-out
0: Disable the reset function of the watchdog timer.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
01: 32
11: 128
WATCHDOG TIMER
Reset Value
0x8021
Initial State
0x80
00
1
00
0
0
1
12-3

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