Samsung S3C2451X User Manual page 458

HS_SPI CONTROLLER
SIGNAL DESCRIPTIONS
The following table lists the external signals between the HS_SPI and external device. All ports of the
HS_SPI can be used as General Purpose I/O ports when disable. See "General Purpose I/O" chapter for
detailed pin configuration.
Channe
Name
l
PSPICLK0
PSPIMISO0
Channel
0
PSPIMOSI0
PSS0
PSPICLK1
PSPIMISO1
Channel
1
PSPIMOSI1
PSS1
OPERATION
The HS_SPI in S3C2451x transfers 1-bit serial data between S3C2451x and external device. The HS_SPI in
S3C2451x supports that CPU or DMA can access to transmit or receive FIFOs separately and to transfer data in
both direction simultaneously. HS_SPI has 2 channel, TX channel and RX channel. TX channel has a path only
from Tx FIFO to external device. RX channel has a path only from external device to RX FIFO.
CPU(or DMA) should write data on the register HS_SPI_TX_DATA to write data in FIFO. Data on the register are
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU(or DMA) should access the register
HS_SPI_RX_DATA and then data are automatically sent to the register HS_SPI_RX_DATA.
OPERATION MODE
HS_SPI has 2 modes, master and slave mode. In master mode, SPICLK is generated and transmitted to external
device. PSS, which is signal to select slave, indicates data valid when it is low level. PSS should be set low before
packets starts to be transmitted or received.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
20-2
Specifications and information herein are subject to change without notice.
Directio
n
Inout PSPICLK0 is the serial clock used to control time to transfer data.
In Master mode, this port is to be input port to get data from slave output
Inout
port. Data are transmitted to master through this port when in slave mode.
In Master mode, this port is to be output port to transfer data from master
Inout output port. Data are received from master through this port when in slave
mode.
As to be slave selection signal, all data TX/RX sequences are executed
Inout
when PSS0 is low.
Inout PSPICLK1 is the serial clock used to control time to transfer data.
In Master mode, this port is to be input port to get data from slave output
Inout
port. Data are transmitted to master through this port when in slave mode.
In Master mode, this port is to be output port to transfer data from master
Inout output port. Data are received from master through this port when in slave
mode.
As to be slave selection signal, all data TX/RX sequences are executed
Inout
when PSS1 is low.
Table 20-1. External signals description
S3C2451X RISC MICROPROCESSOR
Description