Samsung S3C2451X User Manual page 349

S3C2451 RISC MICROPROCESSOR
15
OVERVIEW
The S3C2451X Universal Asynchronous Receiver and Transmitter (UART) provide four independent
asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other
words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The
UART can support bit rates up to 3Mbps bps. Each UART channel contains two 64-byte FIFOs for receiver and
transmitter.
The S3C2451X UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit
insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and a control unit, as shown in Figure 15-1. The
baud-rate generator can be clocked by PCLK, EXTUARTCLK or divided EPLL clock. The transmitter and the
receiver contain 64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter
before being transmitted. The data is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is
shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.
FEATURES
— RxD0, TxD0, RxD1, TxD1, RxD2, TxD2, RxD3 and TxD3 with DMA-based or interrupt-based operation
— UART Ch 0, 1, 2 and 3 with IrDA 1.0 & 64-byte FIFO
— UART Ch 0, 1 and 2 support Auto Flow Control with nRTS0, nCTS0, nRTS1, nCTS1, nRTS2 and nCTS2
signals
— Supports high-speed operation upto 3Mbps
UART
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART
15-1