Samsung S3C2451X User Manual page 152

NAND FLASH CONTROLLER
Figure 7-4. nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram
7.7 NAND FLASH ACCESS
S3C2451X does not support NAND flash access mechanism directly. It only supports signal control mechanism
for NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly.
1. Writing to the command register (NFCMMD) = the NAND Flash Memory command cycle
2. Writing to the address register (NFADDR) = the NAND Flash Memory address cycle
3. Writing to the data register (NFDATA) = write data to the NAND Flash Memory (write cycle)
4. Reading from the data register (NFDATA) = read data from the NAND Flash Memory (read cycle)
5. Reading main ECC registers and Spare ECC registers (NFMECCD0/1, NFSECCD) = read data from the
NAND Flash Memory
In NAND flash access, you must check the RnB status input pin by polling the signal or using interrupt.
7.8 DATA REGISTER CONFIGURATION
1. 8-bit NAND Flash Memory Interface
A. Word Access
Register
NFDATA
B. Half-word Access
Register
NFDATA
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-4
Specifications and information herein are subject to change without notice.
HCLK
nWE / nRE
DATA
Bit [31:24] Bit [23:16]
th
4 I/O[ 7:0] 3
Bit [31:24] Bit [23:16]
Invalid value Invalid value
TWRPH0 TWRPH1
DATA
NOTE:
Bit [15:8]
rd nd
I/O[ 7:0] 2 I/O[ 7:0]
Bit [15:8]
nd
2 I/O[ 7:0]
S3C2451X RISC MICROPROCESSOR
Bit [7:0]
st
1 I/O[ 7:0]
Bit [7:0]
st
1 I/O[ 7:0]