Samsung S3C2451X User Manual page 732

ELECTRICAL DATA
Power
nRESET
XTIpll or
EXTCLK
Clock
Disable
VCO
output
FCLK
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
29-8
Specifications and information herein are subject to change without notice.
PLL can operate after OM[3:2] is latched.
...
PLL is configured by S/W first time.
VCO is adapted to new clock frequency.
...
tRST2RUN
...
MCU operates by XTIpll
or EXTCLK clcok.
Figure 29-6. Power-On Oscillation Setting Timing
tPLL
FCLK is new frequency.
S3C2451X RISC MICROPROCESSOR