Samsung S3C2451X User Manual page 500

HSMMC CONTROLLER
(1) When the end bit of the last data block is sent from the SD Bus to the Host
Controller.
(2) When beginning a wait read transfer at a stop at the block gap initiated by a
Stop At Block Gap Request.
The Host Controller shall wait at the next block gap by driving Read Wait at the start
of the interrupt cycle. If the Read Wait signal is already driven (data buffer cannot
receive data), the Host Controller can wait for current block gap by continuing to
drive the Read Wait signal. It is necessary to support Read Wait in order to use the
suspend / resume function.
(b) In the case of write transactions
This status indicates that a write transfer is executing on the SD Bus. Changes in
this value from 1 to 0 generate a Transfer Complete interrupt in the Normal
Interrupt Status register.
This bit shall be set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing to 1 to Continue Request in the Block Gap Control register to
continue a write transfer.
This bit shall be cleared in either of the following cases:
(1) When the SD card releases write busy of the last data block the Host Controller
shall also detect if output is not busy. If SD card does not drive busy signal for 8 SD
Clocks, the Host Controller shall consider the card drive "Not Busy".
(2) When the SD card releases write busy prior to waiting for write transfer as a
result of a Stop At Block Gap Request.
1 = DAT Line Active
0 = DAT Line Inactive
Data Inhibit (DAT) (ROC)
CMDI [1]
This status bit is generated if either the DAT Line Active or the Read Transfer
NHDA
Active is set to 1. If this bit is 0, it indicates the Host Controller can issue the next
T
SD Command. Commands with busy signal belong to Command Inhibit (DAT) (ex.
R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in
the Normal Interrupt Status register.
Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend
transaction after this bit has changed from 1 to 0.
1 = Cannot issue command which uses the DAT line
0 = Can issue command which uses the DAT line
Command Inhibit (CMD) (ROC)
CMDI [0]
If this bit is 0, it indicates the CMD line is not in use and the Host Controller can
NHCM
issue a SD Command using the CMD line.
D
This bit is set immediately after the Command register (00Fh) is written. This bit is
cleared when the command response is received. Even if the Command Inhibit
(DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0.
Changing from 1 to 0 generates a Command
Complete interrupt in the Normal Interrupt Status register. If the Host Controller
cannot issue the command because of a command conflict error (Refer to
Command CRC Error) or because of Command Not Issued By Auto CMD12
Error, this bit shall remain 1 and the Command Complete is not set. Status issuing
Auto CMD12 is not read from this bit.
1 = Cannot issue command
0 = Can issue command using only CMD line
Note : Buffer Write Enable in Present register should not be asserted for DMA transfers since it generates
Buffer Write Ready interrupt
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-32
Specifications and information herein are subject to change without notice.
S3C2451X RISC MICROPROCESSOR
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