Samsung S3C2451X User Manual page 142

MOBILE DRAM CONTROLLER
MOBILE DRAM CONTROL REGISTER
Register
BANKCON1
BANKCON
BUSY [31]
*
DQSInDLL [30:28]
Reserved [27:26]
Reserved [25:8]
BStop
WBUF
AP
PWRDN
Reserved [3:2]
INIT [1:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
6-10
Specifications and information herein are subject to change without notice.
Address R/W
0x48000004 R/W
Bit
DRAM controller status bit (read only)
0 = IDLE
DQSIn Delay selection
Should be set '3'
Should be '1'
Should be '1'
Read Burst stop control
0= not support Read Burst Stop
[7]
1= support Read Burst Stop
Note: This function is only valid in mDDR interface.
Write buffer control
0 = Disable
[6]
note:
Disabling the write buffer will flush any stored values to the
external DRAM memory.
Auto pre-charge control
0 = Enable auto pre-charge
[5]
Note: If PWRDN is enabled, then AP=0 provides pre-charge
power down and AP=1 provides active power down.
0 = not support DRAM power down control
[4]
1 = support DRAM power down control
Reserved
DRAM initialization control
00 = Normal operation
10 = Issue MRS command
Description
Mobile DRAM control register
Description
1 = BUSY
1 = Enable
1 = Disable auto pre-charge
01 = Issue PALL command
11 = Issue EMRS command
S3C2451X RISC MICROPROCESSOR
Reset Value
0x4400_0040
Initial State
0b
100b
01b
0
0b
1b
0b
0b
00b
00b