Samsung S3C2451X User Manual page 71

S3C2451X RISC MICROPROCESSOR
SOFTWARE RESET
Software can initialize the device state itself when it writes "0x533C_2451" to SWRST register.
During the software reset, the following actions occur :
•
All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state.
•
All pins get their reset state, and BATT_FLT pin is ignored.
•
The nRSTOUT pin is asserted during software reset.
Software reset is invoked then, the following sequence occurs. :
1. User write "0x533C_2451" to SWRST register.
2. System controller request bus controller to finish current transactions.
3. Bus controller send acknowledge to system controller after completed bus transactions.
4. System controller request memory controller to enter into self refresh mode.
5. System controller wait for self refresh acknowledge from memory controller.
6. Internal reset signals and nRSTOUT are asserted and reset counter is activated.
7. Reset counter is expired then, internal reset signals and nRSTOUT are deasserted.
WAKEUP RESET
When S3C2451X is woken up from SLEEP mode by wakeup event, the wakeup reset is invoked. The detail
description will be explained in the power management mode section.
Table 2-1 lists alive registers which are not influenced various reset sources except nRESET. With the exception
of below registers(in table 2-1), All S3C2451X's internal registers are reset by above-mentioned reset sources.
Table 2-1. Registers & GPIO status in RESET (R: reset, S: sustain previous value)
Region
OSCSET , PWRCFG, RSTCON, RSTSTAT, WKUPSTAT, INFORM0,
SYSCON
INFORM1, INFORM2, INFORM3
GPFCON, GPFUDP, GPFDAT, GPGCON[7:0], GPGUDP,
GPIO
GPGDAT[7:0], EXTINT0 ~ EXTINT15
Registers
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER
S S S R
R S R R
2-5