Samsung S3C2451X User Manual page 415

S3C2451X RISC MICROPROCESSOR IIC-BUS INTERFACE
START
Slave Tx mode has been
configured.
IIC detects start signal. and, IICDS
receives data.
IIC compares IICADD and IICDS (the
received slave address).
N
Matched?
Y
The IIC address match
interrupt is generated.
Write data to IICDS.
Clear pending bit to
resume.
Y
Stop?
N
END
The data of the IICDS is
shifted to SDA.
Interrupt is pending.
Figure 18-8. Operations for Slave/Transmitter Mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
18-9
Specifications and information herein are subject to change without notice.