Samsung S3C2451X User Manual page 402

USB2.0 DEVICE
DMA INTERFACE CONTROL REGISTER (DICR)
The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register.
Register Address
DICR 0x4980_0084
DICR Bit
Reserved [31:4]
RELOAD_ [4]
MBAR
Reserved [3:2]
MAX_BURST [1:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-30
Specifications and information herein are subject to change without notice.
R/W
R/W DMA Interface Counter Register
R/W
Reserved
R/W Select Reload Condiion
0 – Every end of Full DMA operation
1 – Every Packet transfer.
Reserved
R/W Max Burst Length
00 = Single transfer
01 = 4-beat incrementing burst transfer(INCR4)
10 = 8-beat incrementing burst transfer(INCR8)
11 = 16-beat incrementing burst transfer(INCR16)
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
Initial State
0
0
0
00