Samsung S3C2451X User Manual page 105

S3C2451X RISC MICROPROCESSOR
USB RESET CONTROL REGISTER (URSTCON)
Register
URSTCON 0x4C00_0088
URSTCON
RESERVED
FUNC_RESET
HOST_RESET
PHY_RESET
USB CLOCK CONTROL REGISTER (UCLKCON)
Register
UCLKCON 0x4C00_008C
MSINTEN
DETECT_VBUS
RESERVED
HOST_CLK_TEST
RESERVED
FUNC_CLK_EN
HOST_CLK_EN
TCLK_EN
Address R/W
R/W
Bit
[31:3] -
[2] Function 2.0 S/W Reset
1: reset
[1] Host 1.1 S/W Reset
1: reset
[0] PHY 2.0 S/W Reset
The PHY_RESET signal must be asserted for at least 10us
1: reset
Address R/W
R/W
Bit
[31] VBUS Detect
This VBUS indicator signal indicates that the VBUS signal on
the USB cable is active. For the serial interface, this signal
controls the pull-up resistance on the D+ line in Device mode
only.
1: Pull-up resistance on the D+ line is enabled based on the
speed of operation.
0: Pull-up resistance on the D+ line is disabled.
[30:5] -
[4] Host CLK Test mode Enable
To ensure correct operations, this field should be set to 1'b1.
0 = Enable
1 = Disable
[3] -
[2] USB 2.0 Function Clock Enable
0 = disable
1 = enable
[1] USB 1.1 Host Clock Enable
0 = disable
1 = enable
[0] USB 2.0 PHY Test Clock Enable
0 = disable
1 = enable
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
USB Reset Control Register
Description
Description
USB Clock Control Register
Description
SYSTEM CONTROLLER
Reset Value
0x0000_0000
Initial State
0
0
0
0
Reset Value
0x0000_0000
Initial State
0
0
0
0
0
0
0
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