Samsung S3C2451X User Manual page 709

S3C2451X RISC MICROPROCESSOR
PCM TIMING
The following figures show the timing relationship for the PCM transfers.
Figure 28-1 shows a PCM transfer with the MSB configured to be coincident with the PCMFSYNC. This MSB
positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 0.
input PCMSOURCE_CLK
output PCMSCLK
output PCMSYNC
output PCMSOUT
PCMSIN
input
internal pcm_irq
(sync to DSP clk)
Figure 28-2 shows a PCM transfer with the MSB configured one shift clock after the PCMFSYNC. This MSB
positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 1.
input PCMSOURCE_CLK
output PCMSCLK
output PCMSYNC
output PCMSOUT
PCMSIN
input
internal pcm_irq
(sync to DSP clk)
Note : In all cases, the PCM shift timing is derived by dividing the input clock, PCMSOURCE_CLK. While the
timing is based upon the PCMSOURCE_CLK, there is no attempt to realign the rising edge of the output
PCMSCLK with the original PCMSOURCE_CLK input clock. These edges will be skewed by internal delay
through the pads as well as the divider logic. This does not represent a problem because the actual shift clock,
PCMSCLK, is output with the data. Furthermore, even if the PCMSCLK output is not used, the skew will be
significantly less than the period of the PCMSOURCE_CLK and should not represent a problem since most PCM
interfaces capture data on the falling edge of the clock.
15
15
Figure 28-1. PCM timing, TX_MSB_POS / RX_MSB_POS = 0
Figure 28-2. PCM timing, TX_MSB_POS / RX_MSB_POS = 1
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
. . .
14 13 1
. . .
14 13 1
. . .
15 14 1
. . .
15 14 1
PCM AUDIO INTERFACE
0 dont care 15
0 dont care 15
datain_reg_valid
0 dont care
0 dont care
datain_reg_valid
14
14
15
15
28-3