Samsung S3C2451X User Manual page 249

S3C2451X RISC MICROPROCESSOR
INTERRUPT SUB MASK (INTSUBMSK) REGISTER
This register has 27 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt
request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the
corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be
serviced.
Register
INTSUBMSK 0X4A00001C
Address R/W
R/W Determine which interrupt source is masked.
The masked interrupt source will not be serviced.
0 = Interrupt service is available.
1 = Interrupt service is masked.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
INTERRUPT CONTROLLER
Reset Value
0xFFFFFFFF
10-23