Samsung S3C2451X User Manual page 41

S3C2451X RISC MICROPROCESSOR
Register Name
DRAM Controller
BANKCFG
BANKCON1
BANKCON2
BANKCON3
REFRESH
TIMEOUT
MATRIX & EBI
BPRIORITY0
BPRIORITY1
EBICON
Memory Controllers ( SSMC )
SMBIDCYR0
SMBIDCYR1
SMBIDCYR2
SMBIDCYR3
SMBIDCYR4
SMBIDCYR5
SMBWSTRDR0
SMBWSTRDR1
SMBWSTRDR2
SMBWSTRDR3
SMBWSTRDR4
SMBWSTRDR5
SMBWSTWRR0
SMBWSTWRR1
SMBWSTWRR2
SMBWSTWRR3
SMBWSTWRR4
SMBWSTWRR5
SMBWSTOENR0
SMBWSTOENR1
SMBWSTOENR2
Table 1-7. S3C2451X Special Registers
Address Reset Value
0x48000000 0x00099F0D
0x48000004 0x00000008
0x48000008 0x00000008
0x4800000C 0x00000008
0x48000010 0x00000020
0x48000014 0x00000000
0X4E800000 0x0000_0004
0X4E800004 0x0000_0004
0X4E800008 0x0000_0004
0x4F000000 0x0000000F
0x4F000020 0x0000000F
0x4F000040 0x0000000F
0x4F000060 0x0000000F
0x4F000080 0x0000000F
0x4F0000A0 0x0000000F
0x4F000004 0x0000001F
0x4F000024 0x0000001F
0x4F000044 0x0000001F
0x4F000064 0x0000001F
0x4F000084 0x0000001F
0x4F0000A4 0x0000001F
0x4F000008 0x0000001F
0x4F000028 0x0000001F
0x4F000048 0x0000001F
0x4F000068 0x0000001F
0x4F000088 0x0000001F
0x4F0000A8 0x0000001F
0x4F00000C 0x00000002
0x4F00002C 0x00000002
0x4F00004C 0x00000002
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Acc. Read/
Unit Write
W R/W Mobile DRAM configuration register
W R/W Mobile DRAM control register
W R/W Mobile DRAM timing control register
W R/W Mobile DRAM (E)MRS Register
W R/W Mobile DRAM refresh control register
W R/W Write Buffer Time out control register
W R/W Matrix Core 0 priority control register
W R/W Matrix Core 1 priority control register
W R/W
W R/W Bank0 idle cycle control register
W R/W Bank1 idle cycle control register
W R/W Bank2 idle cycle control register
W R/W Bank3 idle cycle control register
W R/W Bank4 idle cycle control register
W R/W Bank5 idle cycle control register
W R/W Bank0 read wait state control register
W R/W Bank1 read wait state control register
W R/W Bank2 read wait state control register
W R/W Bank3 read wait state control register
W R/W Bank4 read wait state control register
W R/W Bank5 read wait state control register
W R/W Bank0 write wait state control register
W R/W Bank1 write wait state control register
W R/W Bank2 write wait state control register
W R/W Bank3 write wait state control register
W R/W Bank4 write wait state control register
W R/W Bank5 write wait state control register
Bank0 output enable assertion delay
W R/W
Bank1 output enable assertion delay
W R/W
Bank2 output enable assertion delay
W R/W
PRODUCT OVERVIEW
Function
EBI control register
control register
control register
control register
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