Samsung S3C2451X User Manual page 482

HSMMC CONTROLLER
(1) Set the value corresponding to the executed data byte length of one block to Block Size register.
(2) Set the value corresponding to the executed data block count to Block Count Register.
(3) Set the value corresponding to the issued command to Argument register.
(4) Set the value to Multi / Single Block Select and Block Count Enable. And at this time, set the value
corresponding to the issued command to Data Transfer Direction, Auto CMD12 Enable and DMA Enable.
(5) Set the value corresponding to the issued command to Command register.
Note: When writing the upper byte of Command register, SD command is issued.
(6) And then, wait for the Command Complete Interrupt.
(7) Write 1 to the Command Complete(STACMDCMPLT) in the Normal Interrupt Status register for clearing this
bit.
(8) Read Response register and get necessary information in accordance with the issued command.
(9) In the case where this sequence is for write to a card, go to step (10-W). In case of read from a card, go to
step (10-R).
(10-W) And then wait for Buffer Write Ready Interrupt.
(11-W) Write 1 to the Buffer Write Ready(STABUFWTRDY) in the Normal Interrupt Status register for clearing this
bit.
(12-W) Write block data (in according to the number of bytes specified at the step (1)) to Buffer Data Port register.
(13-W) Repeat until all blocks are sent and then go to step (14).
(10-R) And then wait for the Buffer Read Ready Interrupt.
(11-R) Write 1 to the Buffer Read Ready(STABUFRDRDY) in the Normal Interrupt Status register for clearing this
bit.
(12-R) Read block data (in according to the number of bytes specified at the step (1)) from the Buffer Data Port
register.
(13-R) Repeat until all blocks are received and then go to step (14).
(14) If this sequence is for Single or Multiple Block Transfer, go to step (15). In case of Infinite Block
Transfer, go to step (17).
(15) Wait for Transfer Complete Interrupt.
(16) Write 1 to the Transfer Complete(STATRANCMPLT) in the Normal Interrupt Status register for clearing this
bit.
(17) Perform the sequence for Abort Transaction.
Note: Step (1) and Step (2) can be executed at same time. Step (4) and Step (5) can be executed at same time
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-14
Specifications and information herein are subject to change without notice.
S3C2451X RISC MICROPROCESSOR