Samsung S3C2451X User Manual page 172

NAND FLASH CONTROLLER
7.13.12 MAIN DATA AREA ECC0 STATUS REGISTER
Register Address
NFMECC0 0x4E000034
NFMECC1 0x4E000038
When ECCType is 1-bit ECC
NFMECC0
MECC0_3
MECC0_2
MECC0_1
MECC0_0
NFMECC1
Reserved
NOTE: The NAND flash controller generate NFMECC when read or write main area data while the MainECCLock
(NFCONT[7]) bit is '0'(Unlock).
When ECCType is 4-bit ECC.
NFMECC0 Bit
th
4 Parity [31:24]
rd
3 Parity [23:16]
nd
2 Parity [15:8]
st
1 Parity [7:0]
NFMECC1 Bit
Reserved [31:24]
th
7 Parity [23:16]
th
6 Parity [15:8]
th
5 Parity [7:0]
NOTE: The NAND flash controller generate these ECC parity codes when write main area data while the MainECCLock
(NFCONT[7]) bit is '0' (unlock).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-24
Specifications and information herein are subject to change without notice.
R/W
R NAND Flash ECC status register
R NAND Flash ECC status register
Bit
[31:24] ECC3 for data[7:0]
[23:16] ECC2 for data[7:0]
[15:8] ECC1 for data[7:0]
[7:0] ECC0 for data[7:0]
Bit
[31:0] Reserved
th
4 Check Parity generated from main area
rd
3 Check Parity generated from main area
nd
2 Check Parity generated from main area
st
1 Check Parity generated from main area
Reserved
th
7 Check Parity generated from main area
th
6 Check Parity generated from main area
th
5 Check Parity generated from main area
S3C2451X RISC MICROPROCESSOR
Description
Description
Description
Description
Description
Reset Value
0xXXXXXX
0xXXXXXX
Initial State
0xXX
0xXX
0xXX
0xXX
Initial State
0x00000000
Initial State
0x00
0x00
0x00
0x00
Initial State
0x00
0x00
0x00
0x00