Samsung S3C2451X User Manual page 360

UART
UART FIFO CONTROL REGISTER
There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART
block.
Register
UFCON0 0x50000008
UFCON1 0x50004008
UFCON2 0x50008008
UFCON3 0x5000C008
UFCONn
Tx FIFO Trigger
2)
Level
Rx FIFO Trigger
2)
Level
Reserved
Tx FIFO Reset
Rx FIFO Reset
2)
FIFO Enable
NOTE:
1) At DMA mode, Fifo Enable should be Disabled.
2) Please refer the following recommendation for Interrupt / DMA mode.
Mode
Interrupt mode
DMA mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
15-12
Specifications and information herein are subject to change without notice.
Address R/W
R/W UART channel 0 FIFO control register
R/W UART channel 1 FIFO control register
R/W UART channel 2 FIFO control register
R/W UART channel 3 FIFO control register
Bit
[7:6] Determine the trigger level of transmit FIFO.
00 = Empty
10 = 32-byte
[5:4] Determine the trigger level of receive FIFO.
00 = 1-byte
10 = 16-byte
[3] –
[2] Auto-cleared after resetting FIFO
0 = Normal
[1] Auto-cleared after resetting FIFO
0 = Normal
1)
[0] 0 = Disable
Fifo enable TX fifo Trigger level
Enable 16~48byte
Disable n/a
S3C2451 RISC MICROPROCESSOR
Description
Description
01 = 16-byte
11 = 48-byte
01 = 8-byte
11 = 32-byte
1 = Tx FIFO reset
1 = Rx FIFO reset
1 = Enable
RX fifo Trigger level
8~32byte
n/a
Reset Value
0x0
0x0
0x0
0x0
Initial State
00
00
0
0
0
0
RX time out enable
enable
n/a