Samsung S3C2451X User Manual page 393

S3C2451X RISC MICROPROCESSOR
ENDPOINT CONTROL REGISTER (ECR)
The endpoint control register is useful for controlling an endpoint both in normal operation and test case. Putting
an endpoint in specific operation mode can be accomplished through the endpoint control register.
Register Address
ECR 0x4980_0030
ECR Bit
[31:13]
INPKTHLD [12]
OUTPKTHLD [11]
[10:8]
DUEN [7]
FLUSH [6]
[5:2]
R/W
R/W Endpoint Control Register
R/W
Reserved
R/W The MCU can control Tx FIFO status through this bit. If this
bit is set to one, USB does not send IN data to Host.
0 = The USB can send IN data to Host according to
IN FIFO status(normal operation)
1 = The USB sends NAK handshake to Host
regardless of IN FIFO status.
R/W The MCU can control Rx FIFO Status through this bit. If this
bit is set to one, USB does not accept OUT data from Host.
0 = The USB can accept OUT data from Host
according to OUT FIFO status(normal operation)
1 = The USB does not accept OUT data from Host.
reserved
R/W Dual FIFO mode Enable
0 = Dual Disable(Single mode)
1 = Dual Enable
R/W FIFO Flush
FIFO is flushed when this bit is set to 1.
This bit is automatically cleared after MCU writes 1.
reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
0
0
17-21