Samsung S3C2451X User Manual page 594

CAMERA INTERFACE
FEATURES
— ITU-R BT 601/656 8-bit mode support
— DZI (Digital Zoom In) capability
— Programmable polarity of video sync signals
— Max. 4096 x 4096 pixels input support (non-scaling)
— Max. 2048 x 2048 pixels input support for codec scaling and 720 x 480 pixels input support for preview
scaling
— Image mirror and rotation (X-axis mirror, Y-axis mirror and 180° rotation)
— Preview DMA output image generation (RGB 16/24-bit format)
— Codec DMA output image generation (RGB 16/24-bit format or YCbCr 4:2:0/4:2:2 format)
— Capture frame control support in codec_path
— Scan line offset support in codec_path and preview_path
— YCbCr 4:2:2 codec image format interleave support
— MSDMA supports memory data for preview path input.
— Image effect
EXTERNAL INTERFACE
CAMIF can support the next video standards.
— ITU-R BT 601 YCbCr 8-bit mode
— ITU-R BT 656 YCbCr 8-bit mode
SIGNAL DESCRIPTION
Name
CAMPCLK
CAMVSYNC
CAMHREF
CAMDATA [7:0]
CAMCLKOUT
CAMRESET
CAM_FIELD_A
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
23-2
Specifications and information herein are subject to change without notice.
Table 23-1. Camera interface signal description
I/O Active
I - Pixel Clock, driven by the Camera processor
I H/L Frame Sync, driven by the Camera processor
I H/L Horizontal Sync, driven by the Camera processor
I - Pixel Data driven by the Camera processor
O - Master Clock to the Camera processors
O H/L Software Reset or Power Down for the Camera processor
I - Interlace field (only used in interlace mode)
S3C2451X RISC MICROPROCESSOR
Description