Rcc Control/Status Register (Rcc_Csr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Bit 2 LSEBYP: LSE oscillator bypass

This bit is set and cleared by software to bypass the LSE oscillator. It can be written only

when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

Bit 1 LSERDY: LSE oscillator ready

This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is

0: LSE oscillator not ready

1: LSE oscillator ready

Note: Once the LSEON bit is cleared, this bit goes low after six LSE clock cycles.

Bit 0 LSEON: LSE oscillator enable

This bit is set and cleared by software.

0: LSE oscillator off

1: LSE oscillator on

Note: The LSE clock is directly forwarded to the RTC. To enable the LSE clock to other

RCC control/status register (RCC_CSR)

Address offset: 0x094

Reset value: 0x0C01 C600

(Reset by NRST pad, except reset flags by POR only, not reset by wakeup from Standby)

Access: 0 ≤ wait state ≤ 3, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

system peripherals (USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO,

MSI PLL mode), LSE must be enabled with the LSESYSEN bit.

MSISRANGE[3:0]

RM0453 Rev 1

Reset and clock control (RCC)

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