Control/Status Register (Rcc_Csr) - ST STM32G0 1 Series Reference Manual

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Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability

Set by software to select the LSE oscillator drive capability as follows:

00: low driving capability

01: medium-low driving capability

10: medium-high driving capability

11: high driving capability

Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.

Bit 2 LSEBYP: LSE oscillator bypass

Set and cleared by software to bypass the LSE oscillator (in debug mode).

0: Not bypassed

This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and

Bit 1 LSERDY: LSE oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):

0: Not ready

After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock

Bit 0 LSEON: LSE oscillator enable

Set and cleared by software to enable LSE oscillator:

Control/status register (RCC_CSR)

Up to three wait states are inserted in case of successive accesses to this register. The

Address: 0x60

Reset value: 0xXX00 0000

RM0444 Rev 5

Reset and clock control (RCC)

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