Rcc Clock Control & Status Register (Rcc_Csr) - ST STM32F40 Series Reference Manual

RM0090
Bit 1 LSERDY: External low-speed oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0 LSEON: External low-speed oscillator enable
Set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
6.3.28 RCC clock control & status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
LPWR WWDG IWDG SFT
RSTF RSTF RSTF RSTF
rw rw rw
15 14 13
Bit 31 LPWRRSTF: Low-power reset flag
Bit 30 WWDGRSTF: Window watchdog reset flag
Bit 29 IWDGRSTF: Independent watchdog reset flag
Bit 28 SFTRSTF: Software reset flag
28 27 26 25
POR PIN
BORRS
TF
RSTF RSTF
rw rw rw rw
12 11 10 9
Reserved
Set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
reset.
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Set by hardware when an independent watchdog reset from V
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Doc ID 018909 Rev 4
24 23 22 21
RMVF
rw
8 7 6 5
Reset and clock control for (RCC)
20 19 18
Reserved
4 3 2
Low-power management
domain occurs.
DD
17 16
1 0
LSIRDY LSION
r rw
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