ST STM32G4 Series Reference Manual page 1570

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
•
the FE bit is set by hardware;
•
the invalid data is transferred from the Shift register to the USART_RDR register
(RXFIFO in case FIFO mode is enabled).
•
no interrupt is generated in case of single byte communication. However this bit rises at
the same time as the RXNE bit (RXFNE in case FIFO mode is enabled) which itself
generates an interrupt. In case of multibuffer communication an interrupt will be issued
if the EIE bit is set in the USART_CR3 register.
The FE bit is reset by writing '1' to the FECF in the USART_ICR register.
Note: Framing error is not supported in SPI mode.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of
USART_CR: it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
•
0.5 stop bit (reception in Smartcard mode): no sampling is done for 0.5 stop bit. As a
consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
•
1 stop bit: sampling for 1 stop bit is done on the 8th, 9th and 10th samples.
•
1.5 stop bits (Smartcard mode)
When transmitting in Smartcard mode, the device must check that the data are
correctly sent. The receiver block must consequently be enabled (RE =1 in
USART_CR1) and the stop bit is checked to test if the Smartcard has detected a parity
error.
In the event of a parity error, the Smartcard forces the data signal low during the
sampling (NACK signal), which is flagged as a framing error. The FE flag is then set
through RXNE flag (RXFNE if the FIFO mode is enabled) at the end of the 1.5 stop bit.
Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock
period after the beginning of the stop bit). The 1.5 stop bit can be broken into 2 parts:
one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit
period during which sampling occurs halfway through (refer to
receiver timeout on page 1585
• 2 stop bits
Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit.
The framing error flag is set if a framing error is detected during the first stop bit.
The second stop bit is not checked for framing error. The RXNE flag (RXFNE if the
FIFO mode is enabled) is set at the end of the first stop bit.
1570/2083
for more details).
RM0440 Rev 1
RM0440
Section 36.5.16: USART