ST STM32G4 Series Reference Manual page 1572

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Example 2
To obtain 921.6 Kbaud with usart_ker_ck_pres = 48 MHz:
• In case of oversampling by 16:
USARTDIV = 48 000 000/921 600
BRR = USARTDIV = 52d = 34h
•
In case of oversampling by 8:
USARTDIV = 2 * 48 000 000/921 600
USARTDIV = 104 (104d = 68h)
BRR[3:0] = USARTDIV[3:0] >> 1 = 8h >> 1 = 4h
BRR = 0x64
36.5.8 Tolerance of the USART receiver to clock deviation
The USART asynchronous receiver operates correctly only if the total clock system
deviation is less than the tolerance of the USART receiver.
The causes which contribute to the total deviation are:
•
DTRA: deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
•
DQUANT: error due to the baud rate quantization of the receiver
•
DREC: deviation of the receiver local oscillator
•
DTCL: deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
1572/2083
DTRA + DQUANT + DREC
DWU is the error due to sampling point deviation when the wakeup from low-
power mode is used.
when M[1:0] = 01:
when M[1:0] = 00:
when M[1:0] = 10:
t is the time between the detection of the start bit falling edge and the
WUUSART
instant when the clock (requested by the peripheral) is ready and reaching the
peripheral, and the regulator is ready.
<
+ DTCL + DWU
t
WUUSART
-------------------------- -
DWU =
×
11 Tbit
t
WUUSART
-------------------------- -
DWU =
×
10 Tbit
t
WUUSART
-------------------------- -
DWU =
×
9 Tbit
RM0440 Rev 1
USART receiver tolerance
RM0440