Figure 15.4 Ud Pin Minimum Modulation Width Timing; Figure 15.5 Sci1 Input/Output Timing - Renesas H8/3847R Series Hardware Manual

Section 15 Electrical Characteristics
UD

Figure 15.4 UD Pin Minimum Modulation Width Timing

SCK
SO
1
SI
1
Note: * Output timing reference levels
Output high level
Output low level
See figure 15.9 for the load conditions.
Rev. 6.00 Aug 04, 2006 page 536 of 680
REJ09B0145-0600
V
IL
t
V or V *
IH OH
1
V or V
*
IL OL
t
SCKf
t
SOD
V = 1/2 V
OH
V = 0.8 V
OL

Figure 15.5 SCI1 Input/Output Timing

V
IH
t
UDL UDH
t
scyc
t t
SCKL SCKH
t
SCKr
V
*
OH
V
*
OL
+ 0.2 V
CC
t
SIS
t
SIH