Master Control Register (Mcr) - Renesas H8S Series Hardware Manual

Section 15 Controller Area Network (HCAN)
• Local acceptance filter mask L (LAFML)
• Message control (8 bit × 8 registers × 16 sets) (MC0 to MC15)
• Message data (8 bit × 8 registers × 16 sets) (MD0 to MD15)
• HCAN Monitor Register (HCANMON)
15.3.1

Master Control Register (MCR)

The master control register (MCR) is an 8-bit register that controls the HCAN.
Bit Bit Name Initial Value
7 MCR7 0
6 — 0
5 MCR5 0
4, 3 — All 0
2 MCR2 0
1 MCR1 0
Rev. 6.00 Mar 15, 2006 page 388 of 570
REJ09B0211-0600
R/W Description
R/W HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
R Reserved
This bit is always read as 0. Only 0 should be written
to this bit.
R/W HCAN Sleep Mode
When this bit is set to 1, the HCAN transits to HCAN
sleep mode. When this bit is cleared to 0, HCAN
sleep mode is released.
R Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
R/W Message Transmission Method
0: Transmission order determined by message
identifier priority
1: Transmission order determined by mailbox (buffer)
number priority (TXPR1 > TXPR15)
R/W Halt Request
When this bit is set to 1, the HCAN transits to HCAN
HALT mode. When this bit is cleared to 0, HCAN
HALT mode is released.