Input Reference Selection - Renesas CLK-104a Manual

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual

4. Input Reference Selection

A 4-bit dip-switch (J11) is used to select one of three available reference clocks for the two input clocks of the
RF-PLL (8V19N491-24 or 8V19N882). Two mux devices are used so the two input clocks going to the RF-PLL
device can be selected individually. Please see Dipswitch selection pin allocation below.
Figure 5. Dip-Switch to Individually Select an Input Reference for CLK0/nCLK0 and CLK1/nCLK1
Follow onboard silkscreen labels for "H" or "L" position (see Figure 5) for the Dipswitch (J11) pins. The reference
selection table is as follows.
Table 1. Reference Selections for RF_PLL Inputs (CLK0/nCLK0 and CLK1/nCLK1)
Destination
CLK0_P/N
CLK1_P/N
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
CLK0_SEL0 Pin
H
H
L
L
CLK1_SEL0 Pin
H
H
L
L
CLK0_SEL1 Pin
H
L
H
L
CLK1_SEL1 Pin
H
L
H
L
Reference Selected
X
SMA_IN
TCXO_IN
SFP_RCV_CK_P/N
SFP_RCV_CK_P/N
TCXO_IN
SMA_IN
X
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