Baud Rate Generation - NXP Semiconductors freescale KV4 Series Reference Manual

Match address operation functions in the same way for both MA1 and MA2 registers.
Note that the position of the address mark is the same as the Parity Bit when parity is
enabled for 8 bit and 9 bit data formats.
• If only one of C4[MAEN1] and C4[MAEN2] is asserted, a marked address is
compared only with the associated match register and data is transferred to the
receive data buffer only on a match.
• If C4[MAEN1] and C4[MAEN2] are asserted, a marked address is compared with
both match registers and data is transferred only on a match with either register.

46.5.3 Baud rate generation

A 13-bit modulus counter and a 5-bit fractional fine-adjust counter in the baud rate
generator derive the baud rate for both the receiver and the transmitter. The value from 1
to 8191 written to SBR[12:0] determines the module clock divisor. The SBR bits are in
the UART baud rate registers, BDH and BDL. The baud rate clock is synchronized with
the module clock and drives the receiver. The fractional fine-adjust counter adds
fractional delays to the baud rate clock to allow fine trimming of the baud rate to match
the system baud rate. The transmitter is driven by the baud rate clock divided by 16. The
receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to two sources of error:
• Integer division of the module clock may not give the exact target frequency. This
error can be reduced with the fine-adjust counter.
• Synchronization with the module clock can cause phase shift.
The Table 46-75 lists the available baud divisor fine adjust values.
UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD))
The following table lists some examples of achieving target baud rates with a module
clock frequency of 10.2 MHz, with and without fractional fine adjustment.
Table 46-75. Baud rates (example: module clock = 10.2 MHz)
Bits
Bits
SBR
BRFA
(decimal)
17 00000
16 10011
Freescale Semiconductor, Inc.
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI
Receiver
BRFD value
clock (Hz)
0 600,000.0
19/32=0.59375 614,689.3
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Transmitter
Target Baud
rate
clock (Hz)
37,500.0 38,400
38,418.08 38,400
Error
(%)
2.3
0.047
1313