Input Capture Mode - NXP Semiconductors freescale KV4 Series Reference Manual

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Figure 39-175. Periodic TOF when NUMTOF = 0x00

39.5.4 Input Capture mode

The Input Capture mode is selected when:

• DECAPEN = 0

• COMBINE = 0

• MSnB:MSnA = 0:0, and

• ELSnB:ELSnA ≠ 0:0

When a selected edge occurs on the channel input, the current value of the FTM counter

is captured into the CnV register, at the same time the CHnF bit is set and the channel

interrupt is generated if enabled by CHnIE = 1. See the following figure.

When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive

input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-

capture event. Note that the maximum frequency for the channel input signal to be

detected correctly is system clock divided by 4, which is required to meet Nyquist criteria

for signal sampling.

Writes to the CnV register is ignored in Input Capture mode.

While in BDM, the input capture function works as configured. When a selected edge

event occurs, the FTM counter value, which is frozen because of BDM, is captured into

the CnV register and the CHnF bit is set.

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 39 FlexTimer Module (FTM)