Independent Data Register (Crc_Idr); Control Register (Crc_Cr) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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CRC calculation unit

Independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 General-purpose 8-bit data register bits

Can be used as a temporary storage location for one byte.

This register is not affected by CRC resets generated by the RESET bit in the CRC_CR

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RESET bit

Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF.

This bit can only be set, it is automatically cleared by hardware.

RM0390 Rev 4

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