Crc Registers; Data Register (Crc_Dr); Independent Data Register (Crc_Idr) - ST STM32F40 Series Reference Manual

CRC calculation unit
Each write operation into the data register creates a combination of the previous CRC value
and the new one (CRC computation is done on the whole 32-bit data word, and not byte per
byte).
The write operation is stalled until the end of the CRC computation, thus allowing back-to-
back write accesses or consecutive write and read accesses.
The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the
CRC_CR register. This operation does not affect the contents of the CRC_IDR register.
4.4

CRC registers

The CRC calculation unit contains two data registers and a control
The CRC registers have to be accessed by words (32 bits).
4.4.1

Data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 Data register bits
Used as an input register when writing new data into the CRC calculator.
Holds the previous CRC calculation result when it is read.
4.4.2

Independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:8 Reserved, must be kept at reset value.
87/1422
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
28 27 26 25
12 11 10 9
Reserved
Doc ID 018909 Rev 4
24 23 22 21
DR [31:16]
rw rw rw rw
8 7 6 5
DR [15:0]
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
rw rw rw
register.The peripheral
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
20 19 18 17
4 3 2 1
IDR[7:0]
rw rw rw rw
RM0090
16
rw
0
rw
16
0
rw