Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32F412 Reference Manual

Reset and clock control (RCC) for STM32F412xx
6.3.14 RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 8000
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res. Res.
15 14 13
SPI1
SYSCF
Res. SPI4EN
G EN
rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDM1EN: DFSDM1 clock enable
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SPI5EN:SPI5 clock enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
Bit 16 TIM9EN: TIM9 clock enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
144/1163
28 27 26 25
Res. Res. Res.
12 11 10 9
SDIO
Res. Res.
EN EN
rw rw
Set and cleared by software
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
24 23 22
DFSDM1
Res. Res. Res.
EN
rw
8 7 6
ADC1 USART6
Res. Res.
EN
rw
RM0402 Rev 6
21 20 19 18
TIM11
SPI5EN Res.
EN
rw rw
5 4 3 2
USART1
Res. Res.
EN EN
rw rw
RM0402
17 16
TIM10 TIM9
EN EN
rw rw
1 0
TIM8 TIM1
EN EN
rw rw