Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32F102 Series Reference Manual

Reset and clock control (RCC)
Bit 8 FSMCEN FSMC clock enable
Set and reset by software.
0: FSMC clock disabled
1: FSMC clock enabled
Bit 7 Reserved, always read as 0.
Bit 6 CRCEN CRC clock enable
Set and reset by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5 Reserved, always read as 0.
Bit 4 FLITFEN FLITF clock enable
Set and reset by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3 Reserved, always read as 0.
Bit 2 SRAMEN SRAM interface clock enable
Set and reset by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN DMA2 clock enable
Set and reset by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN DMA1 clock enable
Set and reset by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
6.3.7

APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in APB2 domain
is on going. In this case, wait states are inserted until this access to APB2 peripheral is
finished.
31 30 29
15 14 13
ADC3 TIM8 SPI1
USAR
T1EN
EN EN
rw rw rw
88/690
28 27 26 25
12 11 10 9
TIM1 ADC2 ADC1
EN EN EN EN
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
IOPG IOPF IOPE IOPD
EN EN EN EN
rw rw rw rw
20 19 18 17
4 3 2 1
IOPC IOPB IOPA
Res.
EN EN EN
rw rw rw Res.
RM0008
16
0
AFIO
EN
rw