Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr); For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F40 Series Reference Manual

RM0090
6.3.17

RCC APB2 peripheral clock enable register (RCC_APB2ENR)

for STM32F405xx/07xx and STM32F415xx/17xx

Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
SPI1
SYSCF
Reser- Reser-
G EN
ved ved
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
Bit 16 TIM9EN: TIM9 clock enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Bit 11 SDIOEN: SDIO clock enable
Bit 10 ADC3EN: ADC3 clock enable
28 27 26 25
Reserved
12 11 10 9
SDIO ADC3 ADC2
EN EN EN EN
rw rw rw rw
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Set and cleared by software.
0: SDIO module clock disabled
1: SDIO module clock enabled
Set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled
Doc ID 018909 Rev 4
Reset and clock control for (RCC)
24 23 22 21
8 7 6 5
ADC1 USART6
EN EN
Reserved
rw rw
20 19 18
TIM11 TIM10
EN
rw
4 3 2
USART1 TIM8
EN
Reserved
rw
17 16
TIM9
EN EN
rw rw
1 0
TIM1
EN EN
rw rw
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