Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F410 Reference Manual

Reset and clock control (RCC)
5.3.7

RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res.
15 14 13
SYSCFG
Res. Res.
RST
rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5RST: SPI5RST
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Bit 17 Reserved, must be kept at reset value.
Bit 16 TIM9RST: TIM9 reset
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Bit 11 Reserved, must be kept at reset value.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADC1RST: ADC interface reset
114/771
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
SPI1
Res. Res. Res.
RST
rw
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Set and cleared by software.
0: does not reset TIM11
1: resets TIM11
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Set and cleared by software.
0: does not reset the ADC interface
1: resets the ADC interface
24 23 22
Res. Res. Res. Res.
8 7 6
ADC1 USART6
Res. Res.
RST RST
rw
RM0401 Rev 3
21 20 19 18
SPI5 TIM11
Res.
RST RST
rw rw
5 4 3 2
USART1
Res. Res.
RST
rw rw
RM0401
17 16
TIM9
Res.
RST
rw
1 0
TIM1
Res.
RST
rw