Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32WL5 Series Reference Manual

Reset and clock control (RCC)
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3RST: Low-power timer 3 reset
Bit 5 LPTIM2RST: Low-power timer 2 reset
Bits 4:1 Reserved, must be kept at reset value.
Bit 0 LPUART1RST: Low-power UART 1 reset
7.4.13

RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x040
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
USART1 SPI1
Res. Res.
RST
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: Timer 17 reset
Bit 17 TIM16RST: Timer 16 reset
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Bit 13 Reserved, must be kept at reset value.
316/1461
This bit is set and cleared by software.
0: No effect
1: LPTIM3 reset
This bit is set and cleared by software.
0: No effect
1: LPTIM2 reset
This bit is set and cleared by software.
0: No effect
1: LPUART1 reset
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
TIM1 ADC
Res.
RST RST RST
rw rw rw
This bit is set and cleared by software.
0: No effect
1: TIM17 reset
This bit is set and cleared by software.
0: No effect
1: TIM16 reset
This bit is set and cleared by software.
0: No effect
1: USART1 reset
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 1
21 20 19 18
TIM17
Res. Res. Res.
RST
rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
TIM16
Res.
RST
rw
1 0
Res. Res.