Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F102 Series Reference Manual

RM0008
Bit 2 HSIRDYF HSI ready interrupt flag
Reset by software by writing HSIRDYC.
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
Bit 1 LSERDYF LSE ready interrupt flag
Reset by software by writing LSERDYC.
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
Bit 0 LSIRDYF LSI ready interrupt flag
Reset by software by writing LSIRDYC.
Set by hardware when Internal Low Speed clock becomes stable and LSIRDYDIE is set.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator
6.3.4

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
ADC3 USART1 TIM8
RST RST RST
rw rw rw
Bits 31:16 Reserved, always read as 0.
Bit 15 ADC3RST ADC3 interface reset
Set and reset by software.
0: No effect
1: Reset ADC3 interface
Bit 14 USART1RST USART1 reset
Set and reset by software.
0: No effect
1: Reset USART1
Bit 13 TIM8RST TIM8 timer reset
Set and reset by software.
0: No effect
1: Reset TIM8 timer
28 27 26 25
12 11 10 9
SPI1 TIM1 ADC2 ADC1
RST RST RST RST
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
IOPG IOPF IOPE IOPD
RST RST RST RST
rw rw rw rw
Reset and clock control (RCC)
20 19 18
4 3 2
IOPC IOPB IOPA
Res.
RST RST RST
rw rw rw Res.
17 16
1 0
AFIO
RST
rw
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